Junction field effect transistors (hereinafter referred to as JFETs) are devices having preferable noise characteristics, and a large number of JFETs are used to configure a low noise circuit.
For stable operation of JFETs, it is important to reduce variations in pinch-off voltage, and to reduce the variations, various methods have been proposed. For example, Japanese Patent Publication No. H06-84948 (hereinafter referred to as Document 1) discloses a configuration in which high-concentration gate regions are disposed above and under a channel region specifically in the first embodiment and in FIGS. 3, 4.
FIG. 18 is a cross-sectional view illustrating a semiconductor device disclosed in Document 1. As illustrated in FIG. 18, an epitaxial layer 3 is formed on an n-type embedded layer 2 on a p-type semiconductor substrate 1. Moreover, an insulating region 4 is formed on the semiconductor substrate 1 to surround the embedded layer 2 and the epitaxial layer 3, and an insulating film 6 is formed on a surface of the epitaxial layer 3. In the epitaxial layer 3, a p-type channel region 8 is embedded, and an n-type upper gate region 9 and an n-type lower gate region 9a are formed with the p-type channel region 8 being vertically interposed therebetween.
With the configuration illustrated in FIG. 18, expansion of a depletion layer can be controlled, so that a JFET having low channel resistance and a low pinch-off voltage can be obtained.